Currently, in a lot of chips, a phase delay relationship must be maintained for information exchange between two signals. Taking clock and data as an example, if the clock needs to sample data stably, the rising edge of the clock must have at least a setup time later than the data. However, due to the impact of the manufacturing technique, voltage and temperature (PVT), the delay requirement for these signals may be changed. In addition, the delay of a circuit that implements the delay requirement may be changed. Taking the most basic unit, the NAND gate, as an example, the drive power may turn higher as the temperature turns lower or the voltage turns higher. In this case, the delay time may also turn shorter. To guarantee the delay relationship between signals, the impact of the PVT needs to be compensated. One of compensation methods is using a digital locked loop (DLL). The DLL is used in various circuit systems, especially in high-speed circuits, to dynamically compensate the delay due to the impact of the PVT. The DLL generally consists of two parts: one part is used for dynamically detecting a clock period of the system and the other part is used for implementing a delay according to the detected clock period. In high-speed circuits, the clock period is as short as several nanosecond (ns for short), so that the DLL delay error is less than 100 picosecond (ps for short). With the evolution of technologies and increase of market demands, there are more and more high-speed chips. So, A DLL circuit with high accuracy is required. The DLL circuit generally consists of multiple delay units. The delay time of each delay unit is a delay step value of the DLL.
During the implementation of the present invention, the inventor discovers at least following problem in the prior art: The delay step value of the DLL in the prior art is less accurate, thus failing to meet the requirements for high-frequency circuits that require high accuracy.